1. Technical Field
The present field relates to network switching and more particularly, to methods in controlling internal data transfers in a network switch for a half-duplex Ethernet (IEEE 802.3) packet switched network.
2. Background Art
Switched local area networks use a network switch for supplying data frames between network nodes such as network stations, routers, etc., where each network node is connected to the network switch by a media. The switched local area network architecture uses a media access control (MAC) layer enabling a network interface to access the media. The network switch passes data frames received from a transmitting node to a destination node based on the header information in the received data frame.
Proposals have been made to implement a network switch compliant with IEEE 802.3 by integrating a plurality of MAC devices and physical layer transceivers on a single chip. For example, a single integrated circuit may be configured to include a plurality of media access controllers having respective physical layer transceivers for communication with a network media. The integrated circuit also includes a plurality of transmit and receive buffers for temporarily storing the data for the respective MACs, and a plurality of bus interfaces configured for transferring data packets to and from the respective buffers onto a common bus. Such devices referred to as "Quad-MACs," enable switch designers to implement a network switch by connecting the Quad-MACs to a shared bus serving the network switch fabric.
Such Quad-MAC devices are typically configured to request a DMA transfer on the shared bus when the number of bytes stored in the receive buffer equals the minimum packet size of at least 64 bytes. However, setting the threshold at 64 bytes before data transfer on the shared bus increases the latency of the data packet in the switch. The latency of the data packet is the time delay between the time the data packet is first received by an input network switch port and the time the data is output by an output switch port. Hence, latency increases when data transfer is deferred until at least 64 bytes of a data frame are received before data transfer is initiated.
Although the threshold of the receive buffer (referred to as the receive FIFO watermark) can be reduced to a value less than the minimum data packet length, the switch fabric may end up receiving a collision fragment or a runt packet, at which point the switch fabric needs to filter collision fragments and runt packets from valid data packets. A collision fragment could occur if the network port is connected to a shared medium connecting two network nodes, where the two network nodes simultaneously transmit a data packet on the shared medium.
Hence, reducing the latency by lowering the receive FIFO watermark level which triggers a DMA transfer request places a burden on the host processor to filter collision and runt packets. Hence, the host processor is forced to expend substantial resources analyzing each received stream of packet data to determine whether the received packet data is a valid data packet, or whether the received packet data is either a collision fragment or a runt packet.